`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Wuhan University 
// Engineer: Yu Zihao 
// 
// Create Date: 2021/08/1 18:26:53
// Design Name: 
// Module Name: VDFFE
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module VDFFE #(
  parameter n = 16
)(
    input wire clk,rst,
    input wire [n-1:0] in,
    input wire load,
    output reg [n-1:0] out
    );
    wire [n-1:0] datain;
    assign datain = load ? in : out;
    always @(posedge clk or posedge rst) begin
        if(rst)begin
            out <= {n{1'b0}};
        end else begin
            out <= datain;
        end
    end
endmodule
